Japanese Patent Application Publication No. 2005-209983 (hereinafter referred to as a patent document 1) discloses a semiconductor apparatus having an insulating layer and a plurality of field plates (conductive plates) provided on an upper surface of a peripheral region which is located between an active region (a region in which a MOSFET is formed) and an edge surface of a semiconductor substrate. By providing the field plates on the peripheral region in this manner, an electric field in the peripheral region can be reduced.